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1 ? fn6961.0 isl6323br5381 monolithic dual pwm hybrid controller powering amd svi split-plane and pvi uniplane processors the isl6323br5381 dual pwm controller delivers high efficiency and tight regulation from two synchronous buck dc/dc converters. the isl6323br5381 supports hybrid power control of amd processors which operate from either a 6-bit parallel vid interface (pvi) or a serial vid interface (svi). the dual output isl 6323br5381 features a multi- phase controller to support uniplane vdd core voltage and a single phase controller to power the northbridge (vddnb) in svi mode. only the multi-phase controller is active in pvi mode to support uniplane vdd only processors. a precision uniplane core voltage regulation system is provided by a two-to-four-phase pwm voltage regulator (vr) controller. the integration of two power mosfet drivers, adding flexibility in layout, reduce the number of external components in the multi-phase section. a single phase pwm controller with integr ated driver provides a second precision voltage regulation system for t he north bridge portion of the processor. this monolithic, dual controller with integrated driver solution provides a cost and space saving power management solution. for applications which benefit from load line programming to reduce bulk output capacitors, the isl6323br5381 features output voltage droop. the multi- phase portion also includes advanced control loop featur es for optimal transient response to load apply and removal. one of these features is highly accurate, fully differential, continuous dcr current sensing for load line programming and channel current balance. dual edge modulation is another unique feature, allowing for quicker initial response to high di/dt load transients. the isl6323br5381 supports power savings mode by dropping the number of phases to two when the psi_l bit is set. features ? processor core voltage via integrated multi-phase power conversion ? configuration flexibility - 2-phase operation with internal drivers - 3- or 4-phase operation with external pwm drivers ? psi_l support with phase shedding for improved efficiency at light load ? serial vid interface inputs - two wire, clock and data, bus - conforms to amd 3.4mhz svi specifications ? parallel vid interface inputs - 6-bit vid input - 0.775v to 1.55v in 25mv steps - 0.375v to 0.7625v in 12.5mv steps ? precision core voltage regulation - differential remote voltage sensing - 0.6% system accuracy over-temperature - adjustable reference-voltage offset ? optimal processor core voltage transient response - adaptive phase alignment (apa) - active pulse positioning modulation ? fully differential, continuous dcr current sensing - accurate load line programming - precision channel current balancing ? variable gate drive bias: 5v to 12v ? overcurrent protection ? multi-tiered overvoltage protection ? selectable switching frequency up to 1mhz ? simultaneous digital soft-start of both outputs ? processor northbridge voltage via single phase power conversion ? precision voltage regulation - differential remote voltage sensing - 0.6% system accuracy over-temperature ? serial vid interface inputs - two wire, clock and data, bus - conforms to amd 3.4mhz svi specifications ? overcurrent protection ? continuous dcr current sensing ? variable gate drive bias: 5v to 12v ? simultaneous digital soft-start of both outputs ? selectable switching frequency up to 1mhz ? pb-free (rohs compliant) data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. august 28, 2009
2 fn6961.0 august 28, 2009 pinout isl6323br5381 (48 ld qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6323bcrzr5381 isl6323b crzr 0 to +70 48 ld 7x7 qfn l48.7x7 ISL6323BCRZ-TR5381* isl6323b crzr 0 to +70 48 ld 7x7 qfn l48.7x7 isl6323birzr5381 isl6323b irzr -40 to +85 48 ld 7x7 qfn l48.7x7 isl6323birz-tr5381* isl6323b irzr -40 to +85 48 ld 7x7 qfn l48.7x7 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compat ible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. fb_nb isen_nb- isen4+ isen4- isen3- pvcc_nb comp_nb isen3+ lgate_nb boot_nb ugate_nb isen_nb+ rgnd_nb vid0/vfixen vid1/sel vid2/svd vid3/svc vid4 vid5 vcc pwm4 pwm3 pwrok phase1 ugate1 boot1 lgate1 pvcc1_2 lgate2 boot2 vsen ofs dvc rset fb comp apa isen1+ isen1- isen2+ isen2- en fs rgnd phase_nb vddpwrgd ugate2 phase2 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 49 gnd isl6323br5381 isl6323br5381
3 fn6961.0 august 28, 2009 integrated driver block diagram through shoot- protection boot ugate phase lgate logic control gate pvcc 10k pwm soft-start and fault logic 20k isl6323br5381 isl6323br5381
4 fn6961.0 august 28, 2009 controller block diagram driver vid1/sel offset ofs comp ? 1 n ? pwm1 ? ? boot1 ugate1 phase1 lgate1 boot2 ugate2 phase2 lgate2 pwm3 clock and generator triangle wave soft-start and fault logic fs vddpwrgd gnd ? vid2/svd vid3/svc pwm4 channel current balance pwm2 pwm3 pwm4 isen1- isen1+ i_avg mosfet pwm4 signal logic i_trip pwm3 signal logic channel detect nb_ref rset resistor matching vid0/vfixen svi slave bus e/a rgnd ? fb apa apa vsen ov logic dvc ph3/ph4 por driver mosfet reset power-on oc ch1 current sense isen2- isen2+ ch2 current sense isen3- isen3+ ch3 current sense isen4- isen4+ ch4 current sense isen_nb+ rgnd_nb pvcc_nb driver mosfet pvcc1_2 vcc en lgate_nb boot_nb ugate_nb phase_nb e/a ramp comp_nb nb_ref fb_nb enable logic isen_nb- current sense ? ov logic uv logic en_12v en_12v isen4- isen3- isen4- isen3- pwrok vid4 vid5 uv logic load apply transient enhancement i_avg nb fault logic and pvi dac droop control 2x isl6323br5381 isl6323br5381
5 fn6961.0 august 28, 2009 typical application - svi mode vddpwrgd vfixen svc vcc svd fs ofs dvc cpu en +12v gnd rset +5v isen2- isen2+ isen1- isen1+ fb comp rgnd vsen +12v phase1 ugate1 boot1 lgate1 phase2 ugate2 boot2 lgate2 pvcc1_2 +12v pwm1 vcc boot1 ugate1 phase1 pvcc lgate1 pgnd isl6614 +12v +12v phase_nb ugate_nb boot_nb lgate_nb pvcc_nb +12v +12v boot2 ugate2 phase2 lgate2 pwm2 isen4+ pwm4 isen4- gnd isen3- isen3+ pwm3 load nb load pwrok fb_nb comp_nb isen_nb+ vddnb vdd off on isen_nb- apa +5v vid4 vid5 sel nc nc isl6323br5381 isl6323br5381 isl6323br5381
6 fn6961.0 august 28, 2009 typical application - pvi mode vddpwrgd vid0 vid3 vcc isl6323br5381 vid2 fs ofs dvc cpu en +12v gnd rset +5v isen2- isen2+ isen1- isen1+ fb comp rgnd vsen +12v phase1 ugate1 boot1 lgate1 phase2 ugate2 boot2 lgate2 pvcc1_2 +12v +12v +12v phase_nb ugate_nb boot_nb lgate_nb pvcc_nb +12v +12v isen4+ pwm4 isen4- isen3- isen3+ pwm3 load nb load pwrok fb_nb comp_nb isen_nb+ vddnb vdd off on isen_nb- apa +5v vid4 vid5 vid1/sel nc north bridge regulator disabled in pvi mode pwm1 vcc boot1 ugate1 phase1 pvcc lgate1 pgnd isl6614 boot2 ugate2 phase2 lgate2 pwm2 gnd isl6323br5381 isl6323br5381
7 fn6961.0 august 28, 2009 absolute maximum rati ngs thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.2v supply voltage (pvcc) . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v absolute boot voltage (v boot ). . . . . . . . gnd - 0.3v to gnd + 36v phase voltage (v phase ) . . . . . . gnd - 0.3v to 30v (v boot < 36v) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot-phase = 12v) upper gate voltage (v ugate ). . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lower gate voltage (v lgate ) . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc+ 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to vcc + 0.3v thermal resistance (typical) ja (c/w) jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 27 2 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature isl6323bcrzr5381 . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c isl6323birzr5381 . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. limits established by characteri zation and are not production tested. electrical specifications recommended operating conditions, unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. parameter test conditions min typ max units bias supplies input bias supply current i vcc ; en = high 15 22 25 ma gate drive bias current - pvcc1_2 pin i pvcc1_2 ; en = high 1 1.8 3 ma gate drive bias current - pvcc_nb pin i pvcc_nb ; en = high 0.3 0.9 2 ma vcc por (power-on reset) threshold vcc rising 4.20 4.35 4.50 v vcc falling 3.70 3.85 4.05 v pvcc por (power-on reset) threshold pvcc rising 4.20 4.35 4.50 v pvcc falling 3.70 3.85 4.05 v pwm modulator oscillator frequency accuracy, f sw r t = 100k (0.1%) to ground, (droop enabled) 225 250 265 khz r t = 100k (0.1%) to vcc, (droop disabled), 0c to +70c 245 275 310 khz r t = 100k (0.1%) to vcc, (droop disabled), -40c to +85c 240 275 310 khz typical adjustment range of switching frequency (note 3) 0.08 1.0 mhz oscillator ramp amplitude, v p-p (note 3) 1.50 v maximum duty cycle (note 3) 99.5 % control thresholds en rising threshold 0.80 0.88 0.92 v en hysteresis 70 130 190 mv pwrok input high threshold 1.1 v pwrok input low threshold 0.95 v isl6323br5381 isl6323br5381
8 fn6961.0 august 28, 2009 vddpwrgd sink current open drain, v_vddpwrgd = 400mv 4 ma pwm channel disable threshold v isen3- , v isen4-, v isen2- 4.4 v pin_adjustable offset ofs source current accuracy (positive offset) r ofs = 10k (0.1%) from ofs to gnd 27.5 31 34.5 a ofs sink current accuracy (negative offset) r ofs = 30k (0.1%) from ofs to vcc 50.5 53.5 56.5 a reference and dac system accuracy (vdac > 1.000v) -0.6 0.6 % system accuracy (0.600v < vdac < 1.000v) -1.0 1.0 % system accuracy (vdac < 0.600v) -2.0 2.0 % dvc voltage gain vdac = 1v 2.0 v apa current tolerance v apa = 1v 90 100 108 a error amplifier dc gain r l = 10k to ground (note 3) 96 db gain-bandwidth product (note 3) c l = 100pf, r l = 10k to ground (note 3) 20 mhz slew rate (note 3) c l = 100pf, load = 400a (note 3) 8 v/s maximum output voltage load = 1ma 3.80 4.20 v minimum output voltage load = -1ma 1.3 1.6 v soft-start ramp, vid-on-the-fly (vof) ramp soft-start and vof ramp rate 0c to +85c 2.5 2.8 3.3 mv/s -40c to +85c 2.4 2.8 3.3 mv/s pwm outputs pwm output voltage low threshold i load = 500a 0.5 v pwm output voltage high threshold i load = 500a 4.5 v current sensing - core controller sensed current tolerance v isenn- -v isenn+ = 23.2mv, r set = 37.6k , 4 phases, t a = +25c 68 88 a current sensing - nb controller sensed current tolerance v isen_nb- - v isen_nb+ = 23.2mv, r set = 37.6k , 4 phases, t a = +25c 68 89 a droop current tolerance v isenn- - v isenn+ = 23.2mv, r set = 37.6k , 4 phases, t a = +25c 68 88 a overcurrent protection overcurrent trip level - average channel normal operation, r set = 28.2k 87 100 120 a dynamic vid change (note 3) 130 a overcurrent limiting - individ ual channel normal operation, r set = 28.2k 142 a dynamic vid change (note 3) 190 a power-good core overvoltage threshold vsen rising vdac +225mv vdac + 250mv vdac +275mv electrical specifications recommended operating conditions, unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units isl6323br5381 isl6323br5381
9 fn6961.0 august 28, 2009 core undervoltage threshold vsen falling vdac -325mv vdac -300mv vdac -270mv nb undervoltage threshold isen_nb+ falling vdac -310mv vdac -275mv vdac -235mv power-good hysteresis 50 mv overvoltage protection ovp trip level 1.73 1.80 1.84 v ovp lower gate release threshold 350 400 mv switching time (note 3) [see ?timing diagram? on page 10] ugate rise time t rugate; v pvcc = 12v, 3nf load, 10% to 90% 26 ns lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% 18 ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% 18 ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% 12 ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive 10 ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive 10 ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 15ma source current 2.0 upper drive sink resistance v pvcc = 12v, 15ma sink current 1.65 lower drive source resistance v pvcc = 12v, 15ma source current 1.25 lower drive sink resistance v pvcc = 12v, 15ma sink current 0.80 mode selection vid1/sel input low en taken from lo to hi, vddio = 1.5v 0.6 v vid1/sel input high en taken from lo to hi, vddio = 1.5v 1.00 v pvi interface vidx pull-down vddio = 1.5v 30 40 a vidx input low vddio = 1.5v 0.6 v vidx input high vddio = 1.5v 1.00 v svi interface svc, svd input high (vih) 0.95 v svc, svd input low (vil) 0.4 v schmitt trigger input hysteresis 0.14 0.35 0.45 v svd low level output voltage 3ma sink current 0.285 v maximum svc, svd leakage (note 3) 5 a electrical specifications recommended operating conditions, unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units isl6323br5381 isl6323br5381
10 fn6961.0 august 28, 2009 timing diagram functional pin description vid1/sel this pin selects svi or pvi mode operation based on the state of the pin prior to enabling the isl6323br5381. if the pin is lo prior to enable, the isl6323br5381 is in svi mode and the dual purpose pins [vid0/vfixen , vid2/svc, vid3/svd] use their svi mode related functions. if the pin held hi prior to enable, the isl6323br5381 is in pvi mode and dual purpose pins use their vidx related functions to decode the correct dac code. vid0/vfixen if vid1 is lo prior to enable [svi mode], the pin is functions as the vfixen selection input from the amd processor for determining svi mode versus vfix mode of operation. if vid1 is hi prior to enable [pvi mode], the pin is used as dac input vid0. this pin has an internal 30a pull-down current applied to it at all times. vid2/svd if vid1 is lo prior to enable [svi mode], this pin is the serial vid data bi-directional signal to and from the master device on amd processor. if vid1 is hi prior to enable [pvi mode], this pin is used to decode the programmed dac code for the processor. in pvi mode, this pin has an internal 30a pull-down current applied to it. there is no pulldown current in svi mode. vid3/svc if vid1 is lo prior to enable [s vi mode], this pin is the serial vid clock input from the amd processor. if vid1 is hi prior to enable [pvi mode], the isl6323br5381 is in pvi mode and this pin is used to decode the programmed dac code for the processor. in pvi mode, this pin has an internal 30a pull-down current applied to it. there is no pulldown current in svi mode. vid4 this pin is active only when the isl6323br5381 is in pvi mode. when vid1 is hi prior to enable, the isl6323br5381 decodes the programmed dac voltage required by the amd processor. this pin has an internal 30a pull-down current applied to it at all times. vid5 this pin is active only when the isl6323br5381 is in pvi mode. when vid1 is hi prior to enable, the isl6323br5381 decodes the programmed dac voltage required by the amd processor. this pin has an internal 30a pull-down current applied to it at all times. vcc vcc is the bias supply for the ics small-signal circuitry. connect this pin to a +5v supply and decouple using a quality 0.1f ceramic capacitor. pvcc1_2 the power supply pin for the multi-phase internal mosfet drivers. connect this pin to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple this pin with a quality 1.0f ceramic capacitor. pvcc_nb the power supply pin for the internal mosfet driver for the northbridge controller. connect this pin to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple this pin with a quality 1.0f ceramic capacitor. gnd gnd is the bias and reference ground for the ic. the gnd connection for the isl6323br5381 is through the thermal pad on the bottom of the package. en this pin is a threshold-sensitiv e (approximately 0.85v) system enable input for the controller. held low, this pin disables both core and nb controller operation. pulled high, the pin enables both controllers for operation. when the en pin is pulled high, the isl6323br5381 will be placed in either svi or pvi mode. the mode is determined by the latched value of vid1 on the rising edge of the en signal. a third function of this pin is to provide driver bias monitor for external drivers. a resistor divider with the center tap connected to this pin from t he drive bias supply prevents enabling the controller before insufficient bias is provided to ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate isl6323br5381 isl6323br5381
11 fn6961.0 august 28, 2009 external driver. the resistors should be selected such that when the por-trip point of the ex ternal driver is reached, the voltage at this pin meets the above mentioned threshold level. fs a resistor, placed from fs to ground or from fs to vcc, sets the switching frequency of both controllers. refer to equation 1 for proper resistor calculation. with the resistor tied from fs to ground, droop is enabled. with the resistor tied from fs to vcc, droop is disabled. vsen and rgnd vsen and rgnd are inputs to the core voltage regulator (vr) controller precision diff erential remote-sense amplifier and should be connected to the sense pins of the remote processor core(s), vddfb[h,l]. fb and comp these pins are the internal error amplifier inverting input and output respectively of the core vr controller. fb, vsen and comp are tied together through external r-c networks to compensate the regulator. apa adaptive phase alignment (apa) pin for setting trip level and adjusting time constant. a 100a current flows into the apa pin and by tying a resistor from this pin to comp the trip level for the adaptive phase alignment circuitry can be set. ofs the ofs pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vsen the offset current is generated via an external resistor and precision internal vo ltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. isen1-, isen1+, isen2-, isen2+, isen3-, isen3+, isen4- and isen4+ these pins are used for differentially sensing the corresponding channel output currents. the sensed currents are used for channel balancing, protection, and core load line regulation. connect isen1-, isen2-, isen3-, and isen4- to the node between the rc sense elements surrounding the inductor of their respective channel. tie the isen+ pins to the vcore side of their corresponding channel?s sense capacitor. ugate1 and ugate2 connect these pins to the corresponding upper mosfet gates. these pins are used to control the upper mosfets and are monitored for shoot-through prevention purposes. maximum individual ch annel duty cycle is li mited to 93.3%. boot1 and boot2 these pins provide the bias voltage for the corresponding upper mosfet drives. connect these pins to appropriately-chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc1_2 pin provide the necessary bootstrap charge. phase1 and phase2 connect these pins to the sources of the corresponding upper mosfets. these pins are the return path for the upper mosfet drives. lgate1 and lgate2 these pins are used to control the lower mosfets. connect these pins to the corresponding lower mosfets? gates. pwm3 and pwm4 pulse-width modulation outputs. connect these pins to the pwm input pins of an intersil driver ic if 3- or 4-phase operation is desired. connect the isen- pins of the channels not desired to +5v to disable them and configure the core vr controller for 2- or 3-phase operation. pwrok system wide power-good signal. if this pin is low, the two svi bits are decoded to determine the ?metal vid?. when pin is high, the svi is actively running its protocol. rset connect this pin to vcc through a resistor to set the effective value of the internal risen current se nse resistors. an external ptc thermistor network can also be used to thermally compensate the curren t sense resistors to account for changes in inductor dcr over-temperature . vddpwrgd during normal operation this pin indicates whether both output voltages are within specified overvoltage and undervoltage limits. if either output voltage exceeds these limits or a reset event occurs (such as an overcurrent event), the pin is pulled low. this pin is always low prior to the end of soft-start. rgnd_nb this pin is an input to the nb vr controller precision differential remote-sense amplif ier and should be connected to the sense pin of the north bridge, vddnbfbl. dvc the dvc pin is a buffered version of the reference to the error amplifier. a series resistor and capacitor between the dvc pin and fb pin smooth the voltage transition during vid-on-the-fly operations. fb_nb and comp_nb these pins are the internal error amplifier inverting input and output respectively of the nb vr controller. fb_nb, vdiff_nb, and comp_nb are tied together through external r-c networks to compensate the regulator. r t 10 10.61 1.035 f s () log ? [] = (eq. 1) isl6323br5381 isl6323br5381
12 fn6961.0 august 28, 2009 isen_nb-, isen_nb+ these pins are used for differentially sensing the north bridge output current. the sensed current is used for protection and load line regulation if droop is enabled. connect isen_nb- to the node between the rc sense element surrounding the inductor. tie the isen_nb+ pin to the vnb side of the sense capacitor. ugate_nb connect this pin to the corresponding upper mosfet gate. this pin provides the pwm-controlled gate drive for the upper mosfet and is monitored for shoot-through prevention purposes. boot_nb this pin provides the bias voltage for the corresponding upper mosfet drive. connect this pin to appropriately- chosen external bootstrap capacitor. the internal bootstrap diode connected to the pvcc_nb pin provides the necessary bootstrap charge. phase_nb connect this pin to the source of the corresponding upper mosfet. this pin is the return path for the upper mosfet drive. this pin is used to mo nitor the voltage drop across the upper mosfet for overcurrent protection. lgate_nb connect this pin to the corresponding mosfet?s gate. this pin provides the pwm-controlled gate drive for the lower mosfet. this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower mosfet has turned off. operation the isl6323br5381 utilizes a mu lti-phase architecture to provide a low cost, space saving power conversion solution for the processor core volt age. the controller also implements a simple single phase architecture to provide the northbridge voltage on the same chip. multi-phase power conversion microprocessor load current pr ofiles have changed to the point that the advantages of multi-phase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter that is both cost-effective and thermally viable have forced a change to the cost-saving appr oach of multi-phase. the isl6323br5381 controller helps simplify implementation by integrating vital functions and requiring minimal external components. the ?controller block diagram? on page 4 provides a top level view of the multi-phase power conversion using the isl6323br5381 controller. interleaving the switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. in a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. in addition, the peak-to- peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 2 and 3). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplic ative effect on output ripple frequency. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multi-phase circuit, examine e quation 2, which represents an individual channel peak-to-peak inductor current. in equation 2, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 2 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 3. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output-voltage ripple is a function of capacitance, capacitor figure 1. pwm and inductor-current waveforms for 3-phase converter 1s/div pwm2, 5v/div pwm1, 5v/div il2, 7a/div il1, 7a/div il1 + il2 + il3, 7a/div il3, 7a/div pwm3, 5v/div i p-p v in v out ? () v out lf s v in ----------------------------------------------------- - = (eq. 2) isl6323br5381
13 fn6961.0 august 28, 2009 equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multi-phase topologies can improve overall system cost and size by lo wering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 1.5v to a 36a load from a 12v input. the rms inpu t capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the si ngle-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. figures 25, 26 and 27 in the se ction entitled ?input capacitor selection? on page 33 can be used to determine the input-capacitor rms current based on load current, duty cycle, and the number of channels. they are provided as aids in determining the optimal input capacitor solution. active pulse positioning modulated pwm operation the isl6323br5381 uses a proprietary active pulse positioning (app) modulation sc heme to contro l the internal pwm signals that command each channel?s driver to turn their upper and lower mosfets on and off. the time interval in which a pwm signal can occur is generated by an internal clock, whose cycle time is t he inverse of the switching frequency set by the resistor between the fs pin and ground. the advantage of intersil?s proprietary active pulse positioning (app) modulator is that the pwm signal has the ability to turn on at any point during this pwm time interval, and turn off immediately after the pwm signal has transitioned high. this is important because it allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated wit h other modulation schemes. the pwm output state is driven by the position of the error amplifier output signal, v comp , minus the current correction signal relative to the proprie tary modulator ramp waveform as illustrated in figure 3. at the beginning of each pwm time interval, this modified v comp signal is compared to the internal modulator waveform. as long as the modified v comp voltage is lower then the modulator waveform voltage, the pwm signal is commanded low. the internal mosfet driver detects the low state of the pwm signal and turns off the upper mosfet and turns on the lower synchronous mosfet. when the modified v comp voltage crosses the modulator ramp, the pwm output transitions high, turning off the synchronous mosfet and turning on the upper mosfet. the pwm signal will remain high until the modified v comp voltage crosses the modulator ramp again. when this occurs the pwm signal will transition low again. during each pwm time interval the pwm signal can only transition high once. once pwm transitions high it can not transition high again until the beginning of the next pwm time interval. this prevents the occurrence of double pwm pulses occurring during a single period. to further improve the transient response, isl6323br5381 also implements intersil?s proprietary adaptive phase alignment (apa) technique, which turns on all phases together under transient events with large step current. with both app and apa control, isl6323br5381 can achieve excellent transient performance and reduce the demand on the output capacitors. adaptive phase alignment (apa) to further improve the transient response, the isl6323br5381 also implements intersil?s proprietary adaptive phase alignment (apa) technique, which turns on all of the channels together at the same time during large current step transient events. as figure 3 shows, the apa circuitry works by monitoring the voltage on the apa pin and comparing it to a filtered copy of the voltage on the comp pin. the voltage on the apa pin is a copy of the comp pin voltage that has been negatively offset. if the apa pin exceeds the filtered comp pin voltage an apa event occurs and all of the channels are forced on. i cpp , v in nv out ? () v out lf s v in ----------------------------------------------------------- - = (eq. 3) figure 2. channel input currents and input- capacitor rms current for 3-phase converter channel 1 input current 10a/div channel 2 input current 10a/div channel 3 input current 10a/div input-capacitor current, 10a/div 1s/div isl6323br5381
14 fn6961.0 august 28, 2009 the apa trip level is the am ount of dc offset between the comp pin and the apa pin. this is the voltage excursion that the apa and comp pins must have during a transient event to activate the adaptive phase alignment circuitry. this apa trip level is set through a resistor, r apa , that connects from the apa pin to the comp pin. a 100a current flows across r apa into the apa pin to set the apa trip level as described in equation 4. an apa trip level of 500mv is recommended for most applications. a 0.1f capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. pwm operation the timing of each core channel is set by the number of active channels. channel detection on the isen3- and isen4- pins selects 2-channel to 4-channel operation for the isl6323br5381. the switching cycle is defined as the time between pwm pulse termination signals of each channel. the cycle time of the pu lse signal is the inverse of the switching frequency set by the resistor between the fs pin and ground. the pwm signals command the mosfet driver to turn on/off the channel mosfets. for 4-channel operation, the channel firing order is 1-2-3-4: pwm3 pulse happens 1/4 of a cycle after pwm4, pwm2 output follows another 1/4 of a cycl e after pwm3, and pwm1 delays another 1/4 of a cycle after pwm2. for 3-channel operation, the channel firing order is 1-2-3. connecting isen4- to vcc selects three channel operation and the pulse times are spaced in 1/3 cycle increments. if isen3- is connected to vcc, two channel operation is selected and the pwm2 pulse happens 1/2 of a cycle after pwm1 pulse. continuous current sampling in order to realize proper current-balance, the currents in each channel are sampled continuously every switching cycle. during this time, the cu rrent-sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the isl6323br5381 supports inductor dcr current sensing to continuously sample each channel?s current for channel-current balance. the internal circuitry, shown in figure 4 represents channel n of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on how many channels are operating. inductor windings have a ch aracteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 5. the channel current i ln , flowing through the inductor, passes through the dcr. equation 5 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network across the inductor (r 1 , r 2 and c) extracts the dcr voltage, as sh own in figure 5. the voltage across the sense capacitor, v c , can be shown to be proportional to the channel current i ln , shown in equation 6. where: if the r-c network components are selected such that the rc time constant matches the inductor l/dcr time constant (see equations 7 and 8), then v c is equal to the voltage drop across the dcr multiplied by the ratio of the resistor divider, k. if a resistor divider is not being used, the value for k is 1. figure 3. adaptive phase alignment detection external circuit isl6323br5381 internal circuit comp v apa,trip error apa amplifier c apa r apa + - low filter + - apa pass 100a - + to apa circuitry v apa trip , r apa 100 10 6 ? ? = (eq. 4) figure 4. continuous current sampling time pwm i l i sen switching period v l s () i l n sl dcr + ? () ? = (eq. 5) (eq. 6) v c s () sl ? dcr ------------- 1 + ?? ?? s r 1 r 2 ? () r 1 r 2 + ----------------------- - c ?? 1 + ?? ?? ?? ------------------------------------------------------- - kdcri l n ?? ? = k r 2 r 2 r 1 + -------------------- - = (eq. 7) l dcr ------------- r 1 r 2 ? r 1 r 2 + -------------------- - c ? = (eq. 8) isl6323br5381
15 fn6961.0 august 28, 2009 the capacitor voltage v c , is then replicated across the effective internal sense resistor, r isen . this develops a current through r isen which is proportional to the inductor current. this current, i sen , is continuously sensed and is then used by the controller for load-line regulation, channel-current balancing, and overcurrent detection and limiting. equation 9 shows that the proportion between the channel current, i l , and the sensed current, i sen , is driven by the value of the effective sense resistance, r isen , and the dcr of the inductor. the effective internal r isen resistance is important to the current sensing process because it sets the gain of the load line regulation loop when droop is enabled as well as the gain of the channel-current balance loop and the overcurrent trip level. the effective internal r isen resistance is user programmable and is set through use of the rset pin. placing a single resistor, r set , from the rset pin to the vcc pin programs the effective internal r isen resistance according to equation 10. the north bridge regulator samples the load current in the same manner as the core regulator does. the r set resistor will program all the effective internal r isen resistors to the same value. channel-current balance one important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. by doing this the designer avoids the complexity of driving parallel mosfets and the expense of using expensive he at sinks and exotic magnetic materials. in order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry about the same amount of cu rrent at any load level. to achieve this, the currents through each channel must be sampled every switching cycle. the sampled currents, i n , from each active channel are summed together and divided by the number of active ch annels. the resulting cycle average current, i avg , provides a measure of the total load- current demand on the conver ter during each switching cycle. channel-current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersil?s patented current-balance method is illustrated in figure 6, with error correction for channel 1 repres ented. in the figure, the cycle average current, i avg , is compared with the channel 1 sample, i 1 , to create an error signal i er .the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. vid interface the isl6323br5381 supports hybrid power control of amd processors which operate from either a 6-bit parallel vid interface (pvi) or a serial vid in terface (svi). the vid1/sel pin is used to command the isl6323br5381 into either the pvi mode or the svi mode. whenever the en pin is held low, both the multi-phase core and single-phase north bridge regulators are disabled and the isl6323br5381 is continuously sampling voltage on the vid1/sel pin. when the en pin is toggled high, the stat us of the vid1/sel pin will latch the isl6323br5381 into either pvi or svi mode. this figure 5. inductor dcr current sensing configuration i n isenn- isl6323br5381 internal circuit v in ugate(n) dcr l inductor r 1 v out c out - + v c (s) c i l n - + v l (s) i sen r 2 v c (s) + - isenn+ lgate(n) mosfet driver rset r set - + sample r isen vcc c set (eq. 9) i sen i l dcr r isen ----------------- - ? = (eq. 10) r isen 3 400 --------- - r set ? = figure 6. channel-1 pwm function and current-balance adjustment n i avg i 3 i 2 - + + - + - f(s) pwm1 i 1 v comp i er note: channel 3 and 4 are optional. filter to gate control logic i 4 modulator ramp waveform isl6323br5381
16 fn6961.0 august 28, 2009 latching occurs on the rising edge of the en signal. if the vid1/sel pin is held low during the latch, the isl6323br5381 will be placed into svi mode. if the vid1/sel pin is held high during the latch, the isl6323br5381 will be placed into pvi mode. for the isl6323br5381 to properly enter into either mode, the level on the vid1/sel pin must be stable no less that 1s prior to the en signal transitioning from low to high. 6-bit parallel vid interface (pvi) with the isl6323br5381 in pvi mode, the single-phase north bridge regulator is disabled. only the multi-phase controller is active in pvi mode to support uniplane vdd only processors. table 1 shows the 6-bit parallel vid codes and the corresponding reference voltage. serial vid interface (svi) the on-board serial vid interfac e (svi) circuitry allows the processor to directly drive t he core voltage and northbridge voltage reference level within the isl6323br5381. the svc and svd states are decoded with direction from the pwrok and vfixen inputs as described in the following sections. the isl6323br5381 uses a digital to analog converter (dac) to generate a reference voltage based on the decoded svi value. see figure 7 for a simple svi interface timing diagram. table 1. 6-bit parallel vid codes vid5 vid4 vid3 vid2 vid1 vid0 vref 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 000010 1.5000 000011 1.4750 000100 1.4500 000101 1.4250 000110 1.4000 000111 1.3750 001000 1.3500 001001 1.3250 001010 1.3000 001011 1.2750 001100 1.2500 001101 1.2250 001110 1.2000 001111 1.1750 010000 1.1500 010001 1.1250 010010 1.1000 010011 1.0750 010100 1.0500 010101 1.0250 010110 1.0000 010111 0.9750 011000 0.9500 011001 0.9250 011010 0.9000 011011 0.8750 011100 0.8500 011101 0.8250 011110 0.8000 011111 0.7750 100000 0.7625 100001 0.7500 100010 0.7375 100011 0.7250 100100 0.7125 100101 0.7000 100110 0.6875 100111 0.6750 101000 0.6625 101001 0.6500 101010 0.6375 101011 0.6250 101100 0.6125 101101 0.6000 101110 0.5875 101111 0.5750 110000 0.5625 110001 0.5500 110010 0.5375 110011 0.5250 110100 0.5125 110101 0.5000 110110 0.4875 110111 0.4750 111000 0.4625 111001 0.4500 111010 0.4375 111011 0.4250 111100 0.4125 111101 0.4000 111110 0.3875 111111 0.3750 table 1. 6-bit parallel vid codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vref isl6323br5381
17 fn6961.0 august 28, 2009 pre-pwrok metal vid typical motherboard start-up occurs with the vfixen input low. the controller decodes the svc and svd inputs to determine the pre-pwrok metal vid setting. once the por circuitry is satisfied, the isl6323br5381 begins decoding the inputs per table 2. once the en input exceeds the rising enable threshold, the isl6323br5381 saves the pre-pwrok metal vid value in an on-board holding register and passes this target to the internal dac circuitry. the pre-pwrok metal vid code is decoded and latched on the rising edge of the enable signal. once enabled, the isl6323br5381 passes the pre-pwrok metal vid code on to internal dac circuitry. the internal dac circuitry begins to ramp both the vdd and vddnb planes to the decoded pre-pwrok metal vid output level. the digital soft-start circuitry actually stair steps the internal reference to the target gradually over a fix inte rval. the controlled ramp of both output voltage planes reduces in-rush current during the soft-start interval. at the end of the soft-start interval, the vddpwrgd output transitions high indicating both output planes are within regulation limits. if the en input falls below the enable falling threshold, the isl6323br5381 ramps the internal reference voltage down to near zero. the vddpwrgd deasserts with the loss of enable. the vdd and vddnb planes will linearly decrease to near zero. vfix mode in vfix mode, the svc, svd and vfixen inputs are fixed external to the controller th rough jumpers to either gnd or vddio. these inputs are not expected to change, but the isl6323br5381 is designed to support the potential change of state of these inputs. if vfixen is high, the ic decodes the svc and svd states per table 3. once enabled, the isl6323br5381 begins to soft-start both vdd and vddnb planes to the programmed vfix level. the internal soft-start circuitry slowly stair steps the reference up to the target value and this results in a controlled ramp of the power planes. once soft-start has ended and both output planes are within regulation limits, the vddpwrgd pin transitions high. if the en input falls below the enable falling threshold, then the controller ramps both vdd and vddnb down to near zero. table 2. pre-pwrok metal vid codes svc svd output voltage (v) 00 1.1 01 1.0 10 0.9 11 0.8 figure 7. svi interface timing diagram : typical pre-pwrok metal vid star-tup v_svi v_svi vcc svc svd enable pwrok vdd and vddnb vddpwrgd vfixen 1 3 4 2 5 6 7 8 9 10 11 12 metal_vid metal_vid table 3. vfixen vid codes svc svd output voltage (v) 00 1.4 01 1.2 10 1.0 11 0.8 isl6323br5381
18 fn6961.0 august 28, 2009 svi mode once the controller has su ccessfully soft-started and vddpwrgd transitions high, the northbridge svi interface can assert pwrok to signal the isl6323br5381 to prepare for svi commands. the controller actively monitors the svi interface for set vid commands to move the plane voltages to start-up vid values. details of the svi bus protocol are provided in the amd design guide for voltage regulator controllers accepting serial vid codes specification. once the set vid command is received, the isl6323br5381 decodes the information to determine which plane and the vid target required (see table 4). the internal dac circuitry steps the required output plane voltage to the new vid level. during this time one or both of the planes could be targeted. in the event the core voltage plane, vdd, is commanded to power off by serial vid commands, the vddpwrgd signal remains asserted. the northbridge voltage plane must remain active during this time. if the pwrok input is de-asserted, then the controller steps both vdd and vddnb planes back to the stored pre-pwrok metal vid level in the holding register from initial soft-start. no attempt is made to read the svc and svd inputs during this time. if pwrok is reasserted, then the on-board svi interface waits for a set vid command. if vddpwrgd deasserts during normal operation, both voltage planes are powered down in a controlled fashion. the internal dac circuitry stair steps both outputs down to near zero. table 4. serial vid codes svid[6:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) 000_0000b 1.5500 010_0000b 1.1500 100_0000b 0.7500 110_0000b 0.3500 * 000_0001b 1.5375 010_0001b 1.1375 100_0001b 0.7375 110_0001b 0.3375 * 000_0010b 1.5250 010_0010b 1.1250 100_0010b 0.7250 110_0010b 0.3250 * 000_0011b 1.5125 010_0011b 1.1125 100_0011b 0.7125 110_0011b 0.3125 * 000_0100b 1.5000 010_0100b 1.1000 100_0100b 0.7000 110_0100b 0.3000 * 000_0101b 1.4875 010_0101b 1.0875 100_0101b 0.6875 110_0101b 0.2875 * 000_0110b 1.4750 010_0110b 1.0750 100_0110b 0.6750 110_0110b 0.2750 * 000_0111b 1.4625 010_0111b 1.0625 100_0111b 0.6625 110_0111b 0.2625 * 000_1000b 1.4500 010_1000b 1.0500 100_1000b 0.6500 110_1000b 0.2500 * 000_1001b 1.4375 010_1001b 1.0375 100_1001b 0.6375 110_1001b 0.2375 * 000_1010b 1.4250 010_1010b 1.0250 100_1010b 0.6250 110_1010b 0.2250 * 000_1011b 1.4125 010_1011b 1.0125 100_1011b 0.6125 110_1011b 0.2125 * 000_1100b 1.4000 010_1100b 1.0000 100_1100b 0.6000 110_1100b 0.2000 * 000_1101b 1.3875 010_1101b 0.9875 100_1101b 0.5875 110_1101b 0.1875 * 000_1110b 1.3750 010_1110b 0.9750 100_1110b 0.5750 110_1110b 0.1750 * 000_1111b 1.3625 010_1111b 0.9625 100_1111b 0.5625 110_1111b 0.1625 * 001_0000b 1.3500 011_0000b 0.9500 101_0000b 0.5500 111_0000b 0.1500 * 001_0001b 1.3375 011_0001b 0.9375 101_0001b 0.5375 111_0001b 0.1375 * 001_0010b 1.3250 011_0010b 0.9250 101_0010b 0.5250 111_0010b 0.1250 * 001_0011b 1.3125 011_0011b 0.9125 101_0011b 0.5125 111_0011b 0.1125 * 001_0100b 1.3000 011_0100b 0.9000 101_0100b 0.5000 111_0100b 0.1000 * 001_0101b 1.2875 011_0101b 0.8875 101_0101b 0.4875 * 111_0101b 0.0875 * 001_0110b 1.2750 011_0110b 0.8750 101_0110b 0.4750 * 111_0110b 0.0750 * 001_0111b 1.2625 011_0111b 0.8625 101_0111b 0.4625 * 111_0111b 0.0625 * 001_1000b 1.2500 011_1000b 0.8500 101_1000b 0.4500 * 111_1000b 0.0500 * 001_1001b 1.2375 011_1001b 0.8375 101_1001b 0.4375 * 111_1001b 0.0375 * 001_1010b 1.2250 011_1010b 0.8250 101_1010b 0.4250 * 111_1010b 0.0250 * 001_1011b 1.2125 011_1011b 0.8125 101_1011b 0.4125 * 111_1011b 0.0125 * 001_1100b 1.2000 011_1100b 0.8000 101_1100b 0.4000 * 111_1100b off 001_1101b 1.1875 011_1101b 0.7875 101_1101b 0.3875 * 111_1101b off 001_1110b 1.1750 011_1110b 0.7750 101_1110b 0.3750 * 111_1110b off 001_1111b 1.1625 011_1111b 0.7625 101_1111b 0.3625 * 111_1111b off note: * indicates a vid not required fo r amd family 10h processors. isl6323br5381
19 fn6961.0 august 28, 2009 power savings mode: psi_l bit 7 of the serial vid codes transmitted as part of the 8-bit data phase over the svi bus is allocated for the psi_l. if bit 7 is 0, then the processor is at an optimal load for the regulator to enter power savings mode. if bit 7 is 1, then the regulator should not be in power savings mode. with the isl6323br5381, power savings mode is realized through phase shedding. once a serial vid command with bit 7 set to 0 is received, the isl6323br5381 will shed all phases in a sequential manner until only channel 1 and channel 2 are switching. if active, channel 4 will be shed first, followed by channel 3. when a phase is shed, that phase will not go into a tri-state mode until that phase would have had its pwm go high. when leaving power savings mode, through the reception of a serial vid command with bit 7 set to 1, the isl6323br5381 will sequentially turn on phases starting with phase 3. when a phase is being reactivated, it will not leave a tri-state until the pwm of that phase goes high. if, while in power savings mode, a serial vid command is received that forces a vid level change while maintaining bit 7 at 0, the isl6323br5381 will first exit the power savings mode state as described previously. the output voltage will then be stepped up or down to the appropriate vid level. finally, the isl6323br5381 will then re-enter power savings mode. voltage regulation the integrating compensation network shown in figure 8 insures that the steady-state error in the output voltage is limited only to the error in t he reference voltage and offset errors in the ofs current s ource, remote-sense and error amplifiers. intersil specifies t he guaranteed tolerance of the isl6323br5381 to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is used by the modulator to generate the pwm signals. the pwm signals control the timing of the internal mosfet drivers and regulate the converter output so th at the voltage at fb is equal to the voltage at ref. this will regulate the output voltage to be equal to equation 11. the internal and external circuitry that controls voltage regulati on is illustrated in figure 8. the isl6323br5381 incorporates differential remote-sense amplification in the feedback path. the differential sensing removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage. load-line (droop) regulation by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve a cost-effective solution can help to reduce the output-voltage spike that re sults from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors select ed. by positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 8, with the fs resistor tied to ground, a current 8x the average current of all active channels, 8*i avg , flows from fb through a load-line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage droop with a steady-state value defined as equation 12: the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a function of load current is shown in equation 13. in equation 13, v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, k i is an internal gain determined by the r set resistor connected to the rset pin (k i is defined in equation 10), k is the dc gain of the rc filter across the v out v ref v ofs ? v droop ? = (eq. 11) vid figure 8. output voltage and load-line regulation with offset adjustment 8 i avg external circuit isl6323br5381 internal circuit comp r c r fb fb vsen - + (v droop + v ofs ) error v out v comp c c - + 2k amplifier i ofs ? dac rgnd - + fs r fs droop control to oscillator (eq. 12) v droop i avg r fb ? = (eq. 13) v out v ref v ofs ? i out n ------------- dcr 400 3 --------- - 1 r set --------------- ? ?? ?? kr fb ?? ?? ?? ?? ?? ? = isl6323br5381
20 fn6961.0 august 28, 2009 inductor (k is defined in equation 7), n is the number of active channels, and dcr is the inductor dcr value. output-voltage offset programming the isl6323br5381 allows the designer to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into the fb pin and out of the ofs pin. if r ofs is connected to ground, the voltage across it is regulated to 0.3v, and i ofs flows into the ofs pin and out of the fb pin. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs xr fb ). these functions are shown in figures 9 and 10. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for positive offset (connect r ofs to gnd): for negative offset (connect r ofs to vcc): dynamic vid the amd processor does not step the output voltage commands up or down to the target voltage, but instead passes only the target voltage to the isl6323br5381 through either the pvi or svi interface. the isl6323br5381 manages the resulting vid-on-the-fly transition in a controlled manner, supervis ing a safe output voltage transition without discontinuity or disruption. the isl6323br5381 begins slewing the dac at 3.25mv/s until the dac and target voltage are equal. thus, the total time required for a dynamic vid transition is dependent only on the size of the dac change. to further improve dynamic vid performance, isl6323br5381 also implements a proprietary dac smoothing feature. the external series rc components connected between dvc and fb limit any stair-stepping of the output voltage during a vid-on-the-fly transition. compensating dynamic vid transitions during a vid transition, the resulting change in voltage on the fb pin and the comp pin causes an ac current to flow through the error amplifier compensation components from the fb to the comp pin. this current then flows through the feedback resistor, r fb , and can cause the output voltage to overshoot or undershoot at the end of the vid transition. in order to ensure the smooth trans ition of the output voltage during a vid change, a vid-on-the-fly compensation network is required. this netw ork is composed of a resistor and capacitor in series, r dvc and c dvc , between the dvc and the fb pin. (eq. 14) r ofs 0.3 r fb v offset -------------------------- = (eq. 15) r ofs 1.6 r fb v offset -------------------------- = figure 9. negative offset output voltage programming e/a fb ofs vcc gnd + - + - 0.3v 1.6v vcc r ofs r fb vdiff isl6323br5381 vref v ofs + - i ofs figure 10. positive offset output voltage programming e/a fb ofs vcc gnd + - + - 0.3v 1.6v gnd r ofs r fb v out isl6323br5381 vref v ofs + - i ofs isl6323br5381
21 fn6961.0 august 28, 2009 this vid-on-the-fly compensation network works by sourcing ac current into the fb node to offset the effects of the ac current flowing from the fb to the comp pin during a vid transition. to create th is compensation current the isl6323br5381 sets the voltage on the dvc pin to be 2x the voltage on the ref pin. since the error amplifier forces the voltage on the fb pin and the ref pin to be equal, the resulting voltage across the series rc between dvc and fb is equal to the ref pin voltage. the rc compensation components, r dvc and c dvc , can then be selected to create the desired amount of compensation current. the amount of compensation cu rrent required is dependant on the modulator gain of the system, k1, and the error amplifier r-c components, r c and c c , that are in series between the fb and comp pins. use equations 16, 17 and 18 to calculate the rc component values, r dvc and c dvc , for the vid-on-the-fly com pensation network. for these equations: v in is the input voltage for the power train; v p-p is the oscillator ramp amplitude (1.5v); and r c and c c are the error amplifier r-c components between the fb and comp pins. advanced adaptive zero shoot-through deadtime control (patent pending) the integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfet body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lower mosfet, the phase voltage is monitored until it reaches a -0 .3v/+0.8v (forward/reverse inductor current). at this time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage preventing false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero current, the ugate is released after 35ns delay of the lgate dropping below 0.5v. when lgate first begins to transition low, this quick transition can disturb the phase node and cause a false trip, so there is 20ns of blanking time once lgate falls until phase is monitored. once the phase is high, the advanced adaptive shoot-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to < 1.75v above the phase or the phase falls to < +0.8v, the lgate is released to turn-on. initialization prior to initialization, proper conditions must exist on the en, vcc, pvcc1_2, pvcc_nb, isen3-, and isen4- pins. when the conditions are met, the controller begins soft-start. once the output voltage is within t he proper window of operation, the controller asserts pgood. power-on reset the isl6323br5381 requires vcc, pvcc1_2, and pvcc_nb inputs to exceed their rising por thresholds before the isl6323br5381 has sufficient bias to guarantee proper operation. the bias voltage applied to vcc must reach the internal power-on reset (por) rising threshold. once this threshold figure 11. dynamic vid compensation network isl6323br5381 internal circuit error amplifier c dvc r dvc - + c c r c dvc fb comp r fb vsen i dvc i c i dvc = i c vdac+rgnd k1 v in v p-p ------------ = (eq. 16) a k1 k1 1 ? ---------------- - = r rcomp ar c = (eq. 17) c rcomp c c a ------- - = (eq. 18) figure 12. power sequencing using threshold-sensitive enable (en) external circuit isl6323br5381 internal circuit - + 0.86v en +12v por circuit 10.7k 1.00k enable comparator soft-start and fault logic pvcc1_2 pvcc_nb isen3- vcc isen4- channel detect isl6323br5381
22 fn6961.0 august 28, 2009 is reached, the isl6323br5381 has enough bias to begin checking the driver por inputs, en, and channel detect portions of the init ialization cycle. hyst eresis between the rising and falling thresholds assure the isl6323br5381 will not advertently turn off unless the bias voltage drops substantially (see ?electrica l specifications? on page 7). the bias voltage applied to the pvcc1_2 and pvcc_nb pins power the internal mosfet drivers of each output channel. in order for the isl6323br5381 to begin operation, both pvcc inputs must exceed their por rising threshold to guarantee proper operation of the internal drivers. hysteresis between the rising and falling thresholds assure that once enabled, the isl6323b r5381 will not inadvertently turn off unless the pvcc bias voltage drops substantially (see electrical specifications on page 7). depending on the number of active core channels determined by the phase detect block, the external dr iver por checking is supported by the enable comparator. enable comparator the isl6323br5381 features a dual function enable input (en) for enabling the controller and power sequencing between the controller and external drivers or another voltage rail. the enable comparator holds the isl6323br5381 in shutdown until the voltage at en rises above 0.86v. the enable comparator has about 110mv of hysteresis to prevent bounce. it is important that the driver ics reach their rising por level before the isl6323br5381 becomes enabled. the schematic in figure 12 demonstrates sequencing the isl6323br5381 with the isl66xx family of intersil mosfet drivers, which require 12v bias. when selecting the value of the resistor divider the driver maximum rising por threshold should be used for calculating the proper resistor values. this will prevent improper sequencing events from creating false trips during soft-start. if the controller is configured for 2-phase core operation, then the resistor divider can be used for sequencing the controller with another voltage rail. the resistor divider to en should be selected using a similar approach as the previous driver discussion. the en pin is also used to force the isl6323br5381 into either pvi or svi mode. the mode is set upon the rising edge of the en signal. when the voltage on the en pin rises above 0.86v, the mode will be set depending upon the status of the vid1/sel pin. phase detection the isen3- and isen4- pins are monitored prior to soft-start to determine the number of active core channel phases. if isen4- is tied to vcc, t he controller will configure the channel firing order and timing for 3-phase operation. if isen3- and isen4- are tied to vcc, the controller will set the channel firing order and timing for 2-phase operation (see ?pwm operation? on page 14 for details). soft-start output voltage targets once the por and phase detect blocks and enable comparator are satisfied, t he controller will begin the soft-start sequence and will ramp the core and nb output voltages up to the svi interfac e designated target level if the controller is set svi mode. if set to pvi mode, the north bridge regulator is disabled and the core is soft started to the level designated by the parallel vid code. svi mode prior to soft-starting both core and nb outputs, the isl6323br5381 must check the state of the svi interface inputs to determine the correct target voltages for both outputs. when the controller is enabled, the state of the vfixen, svd and svc inputs are checked and the target output voltages set for both core and nb outputs are set by the dac (see ?serial vid interface (svi)? on page 16). these targets will only change if the en signal is pulled low or after a por reset of vcc. soft-start the soft-start sequence is composed of three periods, as shown in figure 13. at the beginning of soft-start, the dac immediately obtains the output voltage targets for both outputs by decoding the state of the svi or pvi inputs. a 100s fixed delay time, tda, proceeds the output voltage rise. after this delay period the isl6323br5381 will begin ramping both core and nb output voltages to the programmed dac level at a fixed rate of 3.25mv/s. the amount of time required to ramp the output voltage to the final dac voltage is referred to as tdb, and can be calculated as shown in equation 19. after the dac voltage reaches the final vid setting, pgood will be set to high. (eq. 19) tdb v dac 3.25 10 3 ? ------------------------------ = figure 13. soft-start waveforms en 100?s/di vddpwrgd tda tdb v core v nb 400mv/div 400mv/div 5v/div 5v/div isl6323br5381
23 fn6961.0 august 28, 2009 pre-biased soft-start the isl6323br5381 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. the fb pin is mo nitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping reference exceeds the fb pin potential, the output drives ar e enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the dac setting. should the output be pre-charged to a level exceeding the dac setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the dac-set level. both core and nb ou tput support start-up into a pre-charged output. fault monitoring and protection the isl6323br5381 actively monitors both core and nb output voltages and currents to detect fault conditions. fault monitors trigger protective m easures to prevent damage to either load. one common power-good indicator is provided for linking to external system monitors. the schematic in figure 15 outlines the interaction between the fault monitors and the power-good signal. power-good signal the power-good pin (vddpwrgd) is an open-drain logic output that signals whether or not the isl6323br5381 is regulating both nb and core output voltages within the proper levels, and whether any fault conditions exist. this pin should be tied to a +5v source through a resistor. during shutdown and soft-start, vddpwrgd pulls low and releases high after a successful soft-start and both output voltages are operating between the undervoltage and overvoltage limits. pgood transitions low when an undervoltage, overvoltage, or ov ercurrent condition is detected on either regulator output or when the controller is disabled by a por reset or en. in the event of an overvoltage or overcurrent condition, the controller latches off and pgood will not return high. pending a por reset of the isl6323br5381 and successful soft-start, the pgood will return high. overvoltage protection the isl6323br5381 constantly monitors the sensed output voltage on the vsen pin to detect if an overvoltage event occurs. when the output voltage rises above the ovp trip level and exceeds the pgood ov limit actions are taken by the isl6323br5381 to protect the microprocessor load. at the inception of an overvolt age event, both on-board lower gate pins are commanded low as are the active pwm outputs to the external drivers, the pgood signal is driven low, and the isl6323br5381 latches off normal pwm action. this turns on the all of the lower mosfets and pulls the output voltage below a level that might cause damage to the load. the lower mosfets remain driven on until vdiff falls below 400mv. the isl6323br5381 will continue to protect the load in this fashion as long as the overvoltage condition recurs. once an overvoltage condition ends the isl6323br5381 latches off, and must be reset by toggling por, before a soft-start can be re-initiated. figure 14. soft-start waveforms for isl6323br5381-based multi-phase output precharged below dac level output precharged above dac level en v core 400mv/div 5v/div 100s/div isl6323br5381
24 fn6961.0 august 28, 2009 pre-por overvoltage protection prior to pvcc and vcc exceeding their por levels, the isl6323br5381 is designed to protect either load from any overvoltage events that may occur. this is accomplished by means of an internal 10k resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvolt age event ceases or the input power supply cuts off. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. in the event that during norma l operation the pvcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuitry reactivates to protect from any more pre-por overvoltage events. undervoltage detection the undervoltage threshold is set at vdac - 300mv typical. when the output voltage (vsen-rgnd) is below the undervoltage threshold, pgood gets pulled low. no other action is taken by the controller. pgood will return high if the output voltage rises above vdac - 250mv typical. open sense line protection in the case that ei ther of the remote sense lines, vsen or gnd, become open, the isl6323b r5381 is designed to detect this and shut down the controller. this event is detected by monitoring small currents that are fed out the vsen and rgnd pins. in the event of an open se nse line fault, the controller will continue to remain off until the fault goes away, at which point the controller will re-initi ate a soft-start sequence. overcurrent protection the isl6323br5381 takes advantage of the proportionality between the load current and the average current, i avg , to detect an overcurrent condition. see ?continuous current sampling? on page 14 and ?channel-current balance? on page 15 for more detail on how the average current is measured. once the avera ge current exceeds 100a, a comparator triggers the conv erter to begin overcurrent protection procedures. the core regulator and the north bridge regulator have the same ty pe of overcurrent protection. the overcurrent trip threshold is dictated by the dcr of the inductors, the number of active channels, the dc gain of the inductor rc filter and the r set resistor. the overcurrent trip threshold is shown in equation 20. where: equation 20 is valid for both the core regulator and the north bridge regulator. this equation includes the dc load current as well as the total ripple current contributed by all the phases. for the north bridge regulator, n is 1. during soft-start, the overcurrent tr ip point is boosted by a factor of 1.4. instead of comparing the average measured current to 100a, the average current is compared to 140a. immediately after soft-start is over, the comparison level changes to 100a. this is done to allow for start-up into an active load while still supplying output capa citor in-rush current. core regulator overcurrent at the beginning of overcurrent shut down, the controller sets all of the ugate and lgate signals low, puts pwm3 and pwm4 (if active) in a high-impedance state, and forces vddpwrgd low. this turns off all of the upper and lower mosfets. the system remains in this state fo r fixed period of 12ms. if the controller is still enabled at the end of this wait period, it will attempt a soft-start, as shown in figure 16. if th e fault remains, the trip-retry cycles will continue un til either the fa ult is cleared or for a total of seven attempts. if the fault is not cleared on the figure 15. power-good and protection circuitry - - dac - 300mv uv vddpwrgd soft-start, fault and control logic isl6323br5381 internal circuitry - 100a i avg ocp - ocl i 1 repeat for each core channel 142a isen_nb+ - 100a i nb ocp ovp 1.8v nb only core only nb only + + + + + - - dac + 250mv ov vsen ovp 1.8v core only + + - dac - 300mv uv + (eq. 20) i ocp 100 a n dcr ------------- 1 k --- - 3 400 --------- - r set ? ?? ?? v in n ? v out ? 2lf s ?? ---------------------------------------- v out v in --------------- - ? ? ??? = k r 2 r 1 r 2 + -------------------- - = see ?continuous current sampling? on page 14. f sw = switching frequency isl6323br5381
25 fn6961.0 august 28, 2009 final attempt, the controller disables ugate and lgate signals for both core and north bridge and latches off requiring a por of vcc to reset the isl6323br5381. it is important to note that dur ing soft start, the overcurrent trip point is increased by a fact or of 1.4. if the fault draws enough current to trip overcurrent during normal run mode, it may not draw enough current during the soft start ramp period to trip overcurrent while the output is ramping up. if a fault of this type is affecting the output, then the regulator will complete soft start and the trip-retry counter will be reset to zero. once the regulator has completed soft start, the overcurrent trip point will return to it?s nominal setting and an overcurrent shutdown will be initiated. this will result in a continuous hiccup mode. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. north bridge regulator overcurrent the overcurrent shutdown sequen ce for the north bridge regulator is identical to the co re regulator with the exception that it is a single phase regulator and will only disable the mosfet drivers for the north bridge. once 7 retry attempts have been executed unsuccessfully, the controller will disable ugate and lgate signals for both core and north bridge and will latch off requiring a por of vcc to reset the isl6323br5381. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. overcurrent protection in power savings mode while in power savings mode, the ocp trip point will be lower than when running in normal mode. equation 20, with n = 1, will yield the ocp trip point for the core regulator while in power savings mode. if an overcurrent event should occur while the system is in power savings mode, the isl6323br5381 will restart in the normal state with the psi_l bit set to 1. individual channel overcurrent limiting the isl6323br5381 has the ability to limit the current in each individual channel of the core regulator without shutting down the entire regulator. this is accomplished by continuously comparing the sens ed currents of each channel with a constant 140a ocl refe rence current. if a channel?s individual sensed current exceeds this ocl limit, the ugate signal of that channel is immediately forced low, and the lgate signal is forced high. this turns off the upper mosfet(s), turns on the lowe r mosfet(s), and stops the rise of current in that channel, forcing the current in the channel to decrease. that channel?s ugate signal will not be able to return high until the sensed channel current falls back below the 140a reference. general design guide this design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides complete reference designs that include sc hematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circui try, and the maximum amount of load current. generally s peaking, the most economical solutions are those in which each phase handles between 25a and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat si nks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance 0a 0v 3ms/div output current, 50a/div figure 16. overcurrent behavior in hiccup mode output voltage, 500mv/div isl6323br5381
26 fn6961.0 august 28, 2009 (r ds(on) ). in equation 21, i m is the maximum continuous output current, i p-p is the peak-to-peak inductor current (see equation 2), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper- mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 23, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 24, the approximate power loss is p up,2 . a third component involves the lower mosfet reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 . finally, the resistive part of the upper mosfet is given in equation 26 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 23, 24, 25 and 26. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. internal bootstrap device all three integrated drivers feature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 4v and its capacitance value can be chosen from equation 27: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. gate drive voltage versatility the isl6323br5381 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. (eq. 21) p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () ? i lp-p () 2 1d ? () ? 12 --------------------------------------- - + ? = (eq. 22) p low 2 , v don () f s i m n ------ i p-p 2 ----------- + ?? ?? ?? t d1 ? i m n ------ i p-p 2 ----------- ? ?? ?? ?? ?? t d2 ? + ?? = (eq. 23) p up 1 , v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f s ??? p up 2 , v in i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ??? (eq. 24) p up 3 , v in q rr f s ?? = (eq. 25) p up 4 , r ds on () i m n ----- - ?? ?? ?? 2 d ? i p-p 2 12 ---------- + ? (eq. 26) c boot_cap q gate v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ----------------------------------- - n q1 ? = (eq. 27) isl6323br5381
27 fn6961.0 august 28, 2009 package power dissipation when choosing mosfets it is important to consider the amount of power being dissipat ed in the integrated drivers located in the controller. since there are a total of three drivers in the controller pack age, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipatio n in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of +125c. the maximum allowable ic power dissipation for the 7x7 qfn package is approximately 3.5w at room temperature. see ?layout considerations? on page 33 for thermal transfer improvement suggestions. when designing the isl6323br5381 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets and the integrated driver?s internal circuitry and their corresponding average driver current can be estimated with equations 28 and 29, respectively. in equations 28 and 29, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q* vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. the total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. the portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance (p dr_up ), the lower drive path resistance (p dr_up ), and in the boot strap diode (p boot ). the rest of the power will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 18 and 19 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as equation 30: 50nc 20nc figure 17. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 28) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = i dr 3 2 -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 29) figure 18. typical upper-gate drive turn-on path figure 19. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate p dr p dr_up p dr_low p boot i q vcc ? () +++ = (eq. 30) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- = isl6323br5381
28 fn6961.0 august 28, 2009 inductor dcr curren t sensing component selection and r set value calculation with the single r set resistor setting the value of the effective internal sense resistors for both the north bridge and core regulators, it is important to set the r set value and the inductor rc filter gain , k, properly. see ?continuous current sampling? on page 14 and ?channel-current balance? on page 15 for more details on the application of the r set resistor and the rc filter gain. there are 3 separate cases to consider when calculating these component values. if the system under design will never utilize the north bridge regulator and the isl6323 will always be in parallel mode, then follow the instructions for case 3 and only calculate values for core regulator components. for all three cases, use the ex pected vid voltage that would be used at tdc for core and north bridge for the v core and v nb variables, respectively. case 1 in case 1, the dc voltage across the north bridge inductor at full load is less than the dc voltage across a single phase of the core regulator while at full load. here, the dc voltage across the core inductors must be scaled down to match the dc voltage across the north bridge inductor, which will be impressed across the isen_nb pins without any gain. so, the r 2 resistor for the north bridge inductor rc filter is left unpopulated and k = 1. 1. choose a capacitor value for the north bridge rc filter. a 0.1f capacitor is a recommended starting point. 2. calculate the value for resistor r 1 using equation 32: 3. calculate the value for the r set resistor using equation 33 : (derived from equation 20). 4. using equation 34 (also derived from equation 20), calculate the value of k for the core regulator . 5. choose a capacitor value for the core rc filters. a 0.1f capacitor is a recommended starting point. 6. calculate the values for r 1 and r 2 for core. equations 35 and 36 will allow for their computation. case 2 in case 2, the dc voltage across the north bridge inductor at full load is greater than the dc voltage across a single phase of the core regulator while at full load. here, the dc voltage across the north bridge inductor must be scaled down to match the dc voltage across the core inductors, which will be impressed across the isen pins without any gain. so, the r 2 resistor for the core inductor rc filters is left unpopulated and k = 1. 1. choose a capacitor value for the core rc filter. a 0.1f capacitor is a recommended starting point. 2. calculate the value for resistor r 1 : 3. calculate the value for the r set resistor using equation 39 (derived from equation 20). 4. using equation 40 (also derived from equation 20), calculate the value of k for the north bridge regulator . 5. choose a capacitor value for the north bridge rc filter. a 0.1f capacitor is a recommended starting point. 6. calculate the values for r 1 and r 2 for north bridge. equations 41 and 42 will allow for their computation. i nb max dcr nb ? i core max n -------------------------- dcr core ? < (eq. 31) r 1 nb l nb dcr nb c nb ? -------------------------------------- = (eq. 32) (eq. 33) where: k = 1 r set 400 3 --------- - dcr nb k ? 100 a ----------------------------- - i ocp nb v in v nb ? 2l nb f sw ?? --------------------------------- - v nb v in ----------- ? + ?? ?? ?? ?? = (eq. 34) k 3 400 --------- - r set n dcr core ------------------------------ 100 a i ocp core v in n ? v core ? 2l core f sw ?? -------------------------------------------- - v core v in -------------------- ? + ----------------------------------------------------------------------------------------------------------- ?? ? = k r 2 core r 1 core r 2 core + ---------------------------------------------- = (eq. 35) l core dcr core -------------------------- r 1 core r 2 core ? r 1 core r 2 core + ---------------------------------------------- c core ? = (eq. 36) i nb max dcr nb ? i core max n -------------------------- dcr core ? > (eq. 37) r 1 core l core dcr core c core ? ----------------------------------------------- - = (eq. 38) (eq. 39) where: k = 1 r set 400 3 --------- - dcr core k ? 100 a -------------------------------------- - i ocp core v in v core ? 2l core f sw ?? ------------------------------------------ - v core v in -------------------- ? + ?? ?? ?? ?? = (eq. 40) k 3 400 --------- - r set 1 dcr nb --------------------- 100 a i ocp nb v in v nb ? 2l nb f sw ?? --------------------------------- - v nb v in ----------- ? + ------------------------------------------------------------------------------- ?? ? = k r 2 nb r 1 nb r 2 nb + ------------------------------------ - = (eq. 41) (eq. 42) l nb dcr nb --------------------- r 1 nb r 2 nb ? r 1 nb r 2 nb + ------------------------------------ - c nb ? = isl6323br5381
29 fn6961.0 august 28, 2009 case 3 in case 3, the dc voltage across the north bridge inductor at full load is equal to the dc voltage across a single phase of the core regulator while at full load. here, the full scale dc inductor voltages for both north bridge and core will be impressed across the isen pins without any gain. so, the r 2 resistors for the core and nort h bridge inductor rc filters are left unpopulated and k = 1 for both regulators. for this case, it is recommen ded that the overcurrent trip point for the north bridge regulator be equal to the overcurrent trip point for the core regulator divided by the number of core phases. 1. choose a capacitor value for the north bridge rc filter. a 0.1f capacitor is a recommended starting point. 2. calculate the value for the north bridge resistor r 1 : 3. choose a capacitor value for the core rc filter. a 0.1f capacitor is a recommended starting point. 4. calculate the value for the core resistor r 1 : 5. calculate the value for the r set resistor using equation 46: 6. calculate the ocp trip point for the north bridge regulator using equation 47. if the ocp trip point is higher than desired, then the component values must be recalculated utilizing case 1. if the ocp trip point is lower than desired, then the component values must be recalculated utilized case 2. note: the values of r set must be greater than 20k and less than 80k . for all of the 3 cases, if the calculated value of r set is less than 20k , then either the ocp trip point needs to be increased or the inductor must be changed to an inductor with higher dcr. if the r set resistor is greater than 80k , then a value of r set that is less than 80k must be chosen and a resistor divider across both north bridge and core inductors must be set up with proper gain. this gain will represent the variable ?k? in all equations. it is also very important that the r set resistor be tied between the rset pin and the vcc pin of the isl6323. inductor dcr current sensing component fine tuning due to errors in the inductance and/or dcr it may be necessary to adjust the value of r 1 and r 2 to match the time constants correctly. the effect s of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in figure 21. follow the following steps to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. if the regulator is not utilizing droop, modify the circuit by placing the frequency set resistor between fs and ground for the duration of this procedure. 2. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). for example, with l = 1h and dcr = 1m , set the oscilloscope to 500s/div. 3. record v1 and v2 as shown in figure 21. i nb max dcr nb ? i core max n -------------------------- dcr core ? = (eq. 43) r 1 nb l nb dcr nb c nb ? -------------------------------------- = (eq. 44) r 1 core l core dcr core c core ? ----------------------------------------------- - = (eq. 45) (eq. 46) where: k = 1 r set 400 3 --------- - dcr core k ? 100 a -------------------------------------- - i ocp core v in v core ? 2l core f sw ?? ------------------------------------------ - v core v in -------------------- ? + ?? ?? ?? ?? = ( eq. 47 ) i ocp nb 100 a 1 dcr nb --------------------- 3 400 --------- - r set ? ?? ?? v in v nb ? 2l nb f sw ?? --------------------------------- - v nb v in ----------- ? + ?? = figure 20. dcr sensing configuration i n isenn- isl6323br5381 internal circuit v in ugate(n) dcr l inductor r 1 v out c out - + v c (s) c i l n - + v l (s) i sen r 2 v c (s) + - isenn+ lgate(n) mosfet driver rset r set vcc - + sample r isen k i 40k r set ---------------- - = k i 2.4k isl6323br5381
30 fn6961.0 august 28, 2009 4. select new values, r 1,new and r 2,new , for the time constant resistors based on the original values, r 1,old and r 2,old , using equations 48 and 49. 5. replace r 1 and r 2 with the new values and check to see that the error is corrected. repeat the procedure if necessary. loadline regulation resistor the loadline regulation resistor, labeled r fb in figure 8, sets the desired loadline required for the application. equation 50 can be used to calculate r fb . where r isen is the 2.4k internal current sense resistor, k i is defined in equation 10 and k is defined in equation 7. if no loadline regulation is r equired, fs resistor should be tied between the fs pin and vcc. to choose the value for r fb in this situation, please refer to ?compensation without loadline regulation? on page 31. compensation with loadline regulation the load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output f ilter l-c resonant fr equency split with the introduction of current information into the control loop. the final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . since the system poles and zero are affected by the values of the components that are me ant to compensate them, the solution to the system equation becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. treating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. select a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. in equation 51, l is the per-channel filter inductance divided by the number of active channel s; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude as described in the electrical specifications on page 7. once selected, the compensation values in equation 51 assure a stable converter with reasonable transient performance. in mo st cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 51 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 22). keep a position available for c 2 , and be prepared to install a high-frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. figure 21. time constant mismatch behavior v 1 v out i tran v 2 i r 1new , r 1old , v 1 v 2 ---------- - ? = (eq. 48) r 2new , r 2old , v 1 v 2 ---------- - ? = (eq. 49) (eq. 5 0 r fb v droop max 400 3 --------- - i out max n ------------------------- - dcr r set --------------- k ??? --------------------------------------------------------------------- - = figure 22. compensation configuration for load-line regulated isl6323br5381 circuit isl6323br5381 comp c c r c r fb fb vsen c 2 (optional) isl6323br5381
31 fn6961.0 august 28, 2009 compensation without loadline regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 23, provides the necessary compensation. the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. a good general rule is to choose f hf =10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much ph ase shift below the system bandwidth. . in the solutions to the compensation equations, there is a single degree of freedom. for the solutions presented in equation 53, r fb is selected arbitrarily. the remaining compensation components are then selected according to equation 53. in equation 53, l is the per-channel filter inductance divided by the number of active channel s; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude as described in electrical specifications on page 7. 1 2 lc ? ?? ------------------------------- -f 0 > r c r fb 2 f 0 v p-p lc ? ?? ? ? 0.66 v in ? ---------------------------------------------------------- ? = c c 0.66 v in ? 2 v p-p r fb f 0 ?? ? ? ----------------------------------------------------- - = case 1: 1 2 lc ? ?? ------------------------------- - f 0 1 2 c esr ?? ? ------------------------------------- < r c r fb v p-p 2 ? () ? 2 f 0 2 lc ??? 0.66 v in ? ----------------------------------------------------------------- - ? = c c 0.66 v in ? 2 ? () 2 f 0 2 v p-p r fb lc ? ?? ? ? -------------------------------------------------------------------------------------- - = case 2: (eq. 51) f 0 1 2 c esr ?? ? ------------------------------------- > r c r fb 2 f 0 v p-p l ?? ? ? 0.66 v in esr ?? --------------------------------------------- - ? = c c 0.66 v in esr c ?? ? 2 v p-p r fb f 0 l ?? ? ? ? ----------------------------------------------------------------- - = case 3: figure 23. compensation circuit without load-line regulation isl6323br5381 comp c c r c r fb fb vsen c 2 c 1 r 1 c c 0.75 v in 2 f hf lc ? 1 ? ?? ? () ?? 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = r c v p-p 2 ?? ?? ? 2 f 0 f hf lcr fb ?? ??? 0.75 v in 2 f hf lc ? 1 ? ?? ? () ?? ----------------------------------------------------------------------------------------- - = r 1 r fb cesr ? lc ? c esr ? ? ------------------------------------------- - ? = c 1 lc ? c esr ? ? r fb ------------------------------------------- - = c 2 0.75 v in ? 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = (eq. 52) 1 2 lc ? ?? ------------------------------- -f 0 > r c r fb 2 f 0 v p-p lc ? ?? ? ? 0.66 v in ? ---------------------------------------------------------- ? = c c 0.66 v in ? 2 v p-p r fb f 0 ?? ? ? ----------------------------------------------------- - = case 1: 1 2 lc ? ?? ------------------------------- - f 0 1 2 c esr ?? ? ------------------------------------- < r c r fb v p-p 2 ? () ? 2 f 0 2 lc ??? 0.66 v in ? ----------------------------------------------------------------- - ? = c c 0.66 v in ? 2 ? () 2 f 0 2 v p-p r fb lc ? ?? ? ? -------------------------------------------------------------------------------------- - = case 2: (eq. 53) f 0 1 2 c esr ?? ? ------------------------------------- > r c r fb 2 f 0 v p-p l ?? ? ? 0.66 v in esr ?? --------------------------------------------- - ? = c c 0.66 v in esr c ?? ? 2 v p-p r fb f 0 l ?? ? ? ? ----------------------------------------------------------------- - = case 3: isl6323br5381
32 fn6961.0 august 28, 2009 output filter design the output inductors and the output capacitor bank together to form a low-pass filter re sponsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outp ut filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecting the contribution of i nductor current and regulator response, the output voltage in itially deviates by an amount as shown in equation 54 the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see ?interleaving? on page 12 and equation 3), a voltage develops across the bulk capacitor esr equal to i c(p-p ) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance.. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper limit on inductance. equation 56 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 57 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be se lected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in ?mosfets? on page 25, and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple as outlined in ?output filter design? on page 32. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r t . figure 24 and equation 58 are provided to assist in se lecting the correct value for r t . vesl di dt ---- - ? esr i ? + (eq. 54) l esr v in nv ? out ? ?? ?? v out ? f s v in v p-p max () ?? ------------------------------------------------------------------- - ? (eq. 55) l 2ncv o ??? i () 2 --------------------------------- v max iesr ? () ? ? (eq. 56) l 1.25 nc ?? i () 2 ---------------------------- - v max i esr ? () ? v in v o ? ?? ?? ?? (eq. 57) r t 10 10.61 1.035 f s () log ? () ? [] = (eq. 58) isl6323br5381
33 fn6961.0 august 28, 2009 isl6323br5381 input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a four-phase design, use figure 25 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l(p-p) ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. figures 26 and 27 provide the same input rms current information for 3-phase and two-phase designs respectively. use the same approach for selecting the bulk capacitor type and number. low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component selection, layout, and placement minimizes these voltage spikes. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current figure 24. r t vs switching frequency 10 100 1k 10k 100k 1m 10m switching frequency (hz) r t (k ) input-capacitor current (i rms/ i o ) figure 25. normalized input-capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o/ v in ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 26. normalized input-capacitor rms current for 3-phase converter duty cycle (v in/ v o ) 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 27. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o
34 fn6961.0 august 28, 2009 stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using a isl6323br5381 controller. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed first, which include the mosfets, input and output capacitors, and the inductors. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. equidist ant placement of the controller to the core and nb power trains it controls through the integrated drivers helps keep the gate drive traces equally short, resulting in equal trac e impedances and similar drive capability of all sets of mosfets. when placing the mosfets try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input high-frequency capacitors, c hf , should be placed close to the drain of the upper fets and the source of the lower fets. input bulk capacitors, cbulk, case size typically limits following the same rule as the high-frequency input capacitors. place the input bulk capacitors as close to the drai n of the upper fets as possible and minimize the distance to the source of the lower fets. locate the output inductors and output capacitors between the mosfets and the load. the high-frequency output decoupling capacitors (ceramic) should be pl aced as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd next or on the capacitor solder pad. the critical small components include the bypass capacitors (c filter ) for vcc and pvcc, and many of the components surrounding the controller including the feedback network and current sense components. locate the vcc/pvcc bypass capacitors as close to the isl6323br5381 as possible. it is especially impor tant to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recommended. figure 28 shows the connections of the critical components for the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to output induct ors short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they drive the power train mosfets using short, high current pulses. it is important to size them as large and as short as possible to reduce their overall impedance and inductance. they s hould be sized to carry at least one ampere of current (0.02? to 0.05?). going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibilit y of shoot-through. it is also important to route each channels ugate and phase traces in as close proximity as possible to reduce their inductances. current sense component placement and trace routing one of the most critical aspects of the isl6323br5381 regulator layout is the placement of the inductor dcr current sense components and traces. the r-c current sense components must be placed as close to their respective isen+ and isen- pins on the isl6323br5381 as possible. the sense traces that connect the r-c sense components to each side of the output induc tors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. these traces should be routed side by side, and they should be very thin traces. it?s important to route these traces as far away from any other noisy traces or pla nes as possible. these traces should pick up as little noise as possible. thermal management for maximum thermal performanc e in high current, high switching frequency applicatio ns, connecting the thermal gnd pad of the isl6323br5381 to the ground plane with multiple vias is recommended. this heat spreading allows the part to achieve its full thermal potential. it is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part. isl6323br5381
35 fn6961.0 august 28, 2009 vcc isl6323br5381 fs ofs dvc cpu en +12v gnd rset +5v isen2- isen2+ isen1- isen1+ fb comp rgnd vsen +12v phase1 ugate1 boot1 lgate1 phase2 ugate2 boot2 lgate2 pvcc1_2 +12v pwm1 vcc boot1 ugate1 phase1 pvcc lgate1 pgnd isl6614 +12v +12v phase_nb ugate_nb boot_nb lgate_nb pvcc_nb +12v +12v boot2 ugate2 phase2 lgate2 pwm2 isen4+ pwm4 isen4- gnd isen3- isen3+ pwm3 load nb load fb_nb comp_nb isen_nb+ v_nb v_core off on isen_nb- apa +5v via connection to ground plane island on power plane layer island on circuit plane layer key heavy trace on circuit plane layer c in r fs r ofs r set r fb r c c c r apa c 2 c apa r en1 r en2 r c_nb c c_nb c 2_nb r fb_nb r 1_nb c 1_nb c boot_nb c filter c hf c bulk c hf c bulk r 2_1 c 2 c filter c boot c filter c in c in figure 28. printed circuit board power planes and islands red components: locate close to ic to minimize connection path blue components: locate near load (minimize connection path) magenta components: locate close to switching transistors (minimize connection path) c boot c boot c boot c in c in r 1_1 c 1 r 3_1 c 3 r 4_1 c 4 c filter vddpwrgd vfixen svc svd pwrok vid4 vid5 sel nc nc r 2_nb r 2_2 r 4_2 r 1_2 r 3_2 isl6323br5381
36 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6961.0 august 28, 2009 revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 08/25/09 fn6961.0 initial release. isl6323br5381
37 fn6961.0 august 28, 2009 isl6323br5381 package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 4, 10/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05

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